In designing an integrated circuit (IC) device, engineers or designers typically rely on computer design tools to help create an IC schematic or design, including a multitude of individual devices, such as transistors, coupled together to perform a certain function. To actually fabricate the IC device in or on a semiconductor substrate, the IC device schematic must be translated into a physical representation or layout, which itself can then be transferred onto a silicon substrate surface. Computer aided design (CAD) tools, can be used to assist layout designers with translating the discrete circuit elements into shapes, which will embody the devices themselves in the completed IC device. These shapes make up the individual components of the circuit, such as gate electrodes, diffusion regions, metal interconnects.
The software programs employed by the CAD systems to produce layout representations are usually structured to function under a set of predetermined design rules in order to produce a functional circuit. Often, the design rules are determined by certain processing and design limitations based roughly on the patternability of layout designs. For example, design rules may define the space tolerance between devices or interconnect lines.
Once the layout of the circuit has been created, the next step to manufacturing the IC device is to transfer the layout onto a semiconductor substrate. Optical lithography or photolithography is a well-known process for transferring geometric shapes onto the surface on a semiconductor wafer. The photolithography process generally begins with the formation of a photoresist layer on the top surface of a semiconductor substrate or wafer. A reticle or mask having fully light non-transmissive opaque regions, which are usually formed of chrome, and fully light transmissive clear regions, which are usually formed of quartz, is then positioned over the photoresist coated wafer.
The mask is placed between a radiation or light source producing light of a pre-selected wavelength (e.g., ultraviolet light) and an optical lens system, which may form part of a stepper apparatus. When the light from the light source is directed onto the mask, the light is focused to generate a reduced mask image on the wafer, typically using the optical lens system, which contains one or several lenses, filters, and/or mirrors. This light passes through the clear regions of the mask to expose the underlying photoresist layer, and is blocked by the opaque regions of the mask, leaving that underlying portion of the photoresist unexposed. The exposed photoresist layer is then developed, typically through chemical removal of the exposed/non-exposed regions of the photoresist layer. The end result is a semiconductor wafer coated with a photoresist layer exhibiting a desired pattern, which defines the geometries, features, lines and shapes of that layer. This pattern can then be used for etching underlying regions of the wafer.
There is a pervasive trend in the art of IC design and fabrication to increase the density with which various structures are arranged. For example, linewidths and separation between lines is becoming increasingly smaller. With this size reduction, however, various steps within the integrated circuit design and fabrication process become more difficult. For example, as mentioned above, IC device schematics are translated into a layout representation under a set of predetermined design rules. Currently, IC layout design rules are based roughly on the patternability of layout designs, without taking into account many of the layout interactions. This may result in patterns that are “clean” to geometric layout rules, but are very susceptible to bridging or pinching, or patterns that no longer follow desired layer-to-layer expectations due to rounding, end pullback, and/or other interactions not contemplated or otherwise accounted for by the original predetermined design rules. In addition, design rules are often very general (e.g., polysilicon must extend beyond the active layer). However, as the technology continues to shrink, these general design rules do not account for layout interactions. Such problems can exist with respect to providing an optimized layout for a current process technology as well as expanding into a next generation process technology, thereby jeopardizing critical dimension capabilities.
Accordingly, a need exists in the art for a system and method for design rule creation and selection.